1. Field of the Invention
The present invention relates to an improvement of a data comparator used in a TLB (Translation Look-aside Buffer).
2. Description of the Related Art
A conventional data comparator used in a TLB has an arrangement shown in FIG. 1 or 2.
The data comparator in FIG. 1 is constituted by one sense line SL, a precharge p-channel MOSFET TP connected between a precharge power supply terminal Vcc and the sense line SL, and a plurality of bit comparators CMP.
A precharge signal .phi.p is applied to the gate of the p-channel MOSFET TP, and a potential of an active level "L" is applied to this gate for a predetermined period. A ground terminal Vss may be connected to the gate of the p-channel MOSFET TP such that a ground potential is always applied to the gate.
Each of the bit comparators CMP has a memory for storing predetermined bit data. Each of the bit comparators CMP compares the bit data with one bit of comparison data A0 to An supplied outside the bit comparators CMP. As a result, when the bit data coincides with one bit of the comparison data A0 to An, the bit comparator CMP outputs the comparison result to the sense line SL.
However, in the data comparator of FIG. 1 , the output terminals of the bit comparators CMP are connected to one sense line SL. For this reason, when the number of bits of comparison data is increased, the number of the bit comparators CMP is increased. As a result, a load capacitance of the sense line SL is considerably increased. In fact, when the number of bits of the comparison data is several tens, the load capacitance of the sense line SL poses a problem.
First, the data comparator of FIG. 1 requires a long time for precharging the sense line SL by the precharge MOSFET TP. Second, when the output result obtained from one of the bit comparators CMP is different from output results obtained from the remaining bit comparators CMP, a time for defining the output result of the bit comparator CMP is disadvantageously increased.
In the data comparator of FIG. 2, comparison data is constituted by a plurality of groups (A0 to A3), (A4 to A7), (A8 to A7), (A8 to A11), . . . , (An-3 to An). Each of sense lines SL is arranged in each of the groups. As in FIG. 1, a precharge MOSFET TP is connected between a precharge power supply terminal Vcc and the sense lines SL. In addition, each of bit comparators CMP is connected to each one bit of the comparison data A0 to An, and each of the bit comparators CMP is connected to the sense line SL of the group to which corresponding bit comparators belong.
The sense lines SL are connected to the input terminals of a logic gate circuit GT. This logic gate circuit GT outputs comparison results obtained by comparing the bit data with the comparison data A0 to An.
However, in the data comparator of FIG. 2, when the number of bits of the comparison data is increased, the number of the sense lines SL is increased accordingly. For this reason, the logic gate GT having a large number of input terminals is required. Therefore, when the number of bits of the comparison data becomes, e.g., about several tens, a comparison result output speed is decreased, and the comparison results cannot be detected.